The present invention generally relates to 3D assembly, and more specifically to 3D assemblies which compensate for interposer bow. The 3D assemblies includes interposers, a laminate and processor chips.
Three-dimensional (3D) integration semiconductor assembly using through-silicon-vias (TSV) and solder bumps provides benefits such as increasing both packaging density and bandwidth due to the short connection lengths.
Silicon interposer warpage during the conventional reflow processes may result in non-wetting of solder bumps and/or bridging between solder joints, thereby decreasing the assembly yield. This influence may become more significant when the chip size increases and the silicon interposer thickness decreases.
For example, FIG. 1 illustrates a conventional bonding process of a silicon interposer 100 with an organic laminate 110. As depicted in the left hand side of FIG. 1, each of an incoming interposer chip 100 and an organic laminate 110 are not perfectly flat. Specifically, the interposer 100 and the laminate 110 are bowed in opposing directions. Subsequently, the interposer chip 100 and organic laminate 110 are placed together and a reflow process (represented by the arrow) takes place. Referring to the right side of FIG. 1, after reflow, the interposer 100 and laminate 110 may not touch. For example, the center region of the interposer fails to make physical contact with the laminate 110, which may result in one or more open connections. Conversely, the edges of the chip may come too close to the laminate surface causing solder ball bridging or shorting.
Therefore, a need exists to mitigate the above described bowing and bridging associated with packaging processes.